Modern electronic systems that are implemented in application-specific integrated circuits (ASICs), field-programmable integrated circuits (FPGAs), or complex programmable logic devices (CPLDs) are often extremely complex, requiring years of effort to realize. For this reason, it is common to decompose the design problem into phases: a specification phase in which the functional requirements of the system are defined, a modeling phase in which an executable version of the functional description is realized, and an implementation phase in which a hardware realization of the system is created. For the end result to be correct, each phase must faithfully implement the result of the previous phase. For example, the hardware realization must exactly mirror the functional model created during the modeling phase. In practice, validating that implementations are faithful, which is the greatest part of the design effort, often exposes design flaws or faulty assumptions upstream. This, in turn, results in reworking the earlier design representation.
The modeling phase consists of capturing the design in an executable form, simulating, then analyzing the results. The modeling phase is appropriate for algorithm exploration, in which system parameters such as sample rates, data precision, and choice of functional blocks are decided. This process is iterative, with the results of analysis leading to revisions that allow system specifications to be met. In the modeling phase, a high level of abstraction is desirable in order to facilitate algorithm exploration. For example, it is common to represent arithmetic values using floating point or fixed point rather than as buses of logic signals. Sampled data systems are also most conveniently modeled by defining sample rates rather than using explicit interconnections (“wires”) representing clock and associated control signals (e.g., enable, reset).
The implementation phase consists of creating a low-level hardware realization of the system in terms of primitives in an appropriate technology library. Hardware description languages such as VHDL and Verilog are commonly used for such a representation. In this representation, high level constructs such as sample rates and arithmetic values must be implemented in terms of clock signals and buses of logic vectors, and functional operators (e.g., discrete Fourier transform) must be mapped into appropriate circuitry. To achieve high performance, libraries of intellectual property (IP) blocks are commonly used. Such IP blocks are typically custom built to be efficient in the target technology.
Electronic systems that include an embedded microprocessor or microcontroller are quite common. The processor is often coupled to peripherals that expand the functionality of the electronic system. Communication between the processor and peripherals traditionally takes place over a shared bus.
A typical design task is to take an existing IP block and integrate the block into the system by connecting the block to the bus. The block often requires additional interface logic that sits between the bus and the block. The interface logic enables communication between the bus and the block, and must be customized to meet the input/output (I/O) requirements of the block. In addition, the interface logic may need to be customized to meet certain requirements set forth in the system-level specification, e.g., to use a memory map address range allocated to the peripheral.
In some instances, a designer may understand the IP block but not know how to create the logic that connects the block to the bus. Solving the problem requires that the designer call on others for help or spend valuable time learning the bus protocol.
A system and method that address the aforementioned problems, as well as other related problems, are therefore desirable.